The present invention relates to a semiconductor device, and provides a technique applicable to a semiconductor device including, for example, interconnections.
In one DRAM configuration, a bit line is disposed in a layer below a capacitive element. For example, as described in Japanese Unexamined Patent Application Publication No. 2002-134477 (JP-A-2002-134477), the bit line in such a configuration typically has a structure where a tungsten layer is stacked on a titanium nitride layer. In JP-A-2002-134477, the bit line is provided on a silicon oxide film.